How do electronic switches produce a yes or no?
Computers often use two ranges of voltage to represent 0 and 1. A logic gate is a small group of input-controlled electronic switches. Their connections determine the output rule.
Start with inversion: a low input pulls the output high, and a high input pulls it low. Then compare switches in series and in parallel to see why some paths need both conditions and others need only one.
Changing the output takes time. During a change, its voltage may not reliably count as either 0 or 1. The picture marks that interval X, rather than inventing a random third digit.
Stop partway through a transition
- Change the input. Which switch path turns on, and does the output rise or fall?
- Pause during a change. Why might the output be marked X?
- Increase capacitance and compare the change time. Connect another stage and watch the order of responses.
A connected network, continuous charge
Further controls and numerical checks
- Enter exploration, select the initial and new inputs, then move sample time. Keeping the same inputs does not invent a transition.
- Choose NAND and change
00to10, then try11. Follow the connected channels and watch whether the output actually discharges. - With the inverter and supply unchanged, increase capacitance from 10 fF to 40 fF. The time to half supply becomes four times longer on the same time axis.
- Select the inverter and connect the next stage. Y₁ crosses the model boundary before Y₂ begins changing. Selecting another gate exits the cascade view.
- Reset restores gate type, both input pairs, capacitance, both channel resistances, supply, sample time and cascade connection. Native buttons and ranges support keyboard operation.
A solid channel means enabled; a dashed channel means disabled. An enabled channel need not carry steady current. Once the node settles at a rail, charging or discharging current tends to zero in this ideal model. The violet column indicates V/VDD; it is not a fluid or a separate charge simulation. Physical time is calculated in picoseconds and slowed for viewing.
Want to check the technical details?
A computer commonly represents 0 and 1 using different voltage ranges. A logic gate is a small arrangement of electronic switches controlled by its inputs. Start with the simplest rule: a low input makes the output rise; a high input makes it fall. The change takes a little time.
Start with the inverter. A low input enables the upper pMOS path and disables the lower nMOS path. The output capacitance charges through the pull-up. A high input swaps the paths, allowing that capacitance to discharge through the pull-down. The input controls an insulated gate; its wire does not deliver direct current through the insulation into the channel.
The Boolean function tells us the eventual destination. It does not make the output voltage jump there. A rising output can still read 0, then pass through an X region, before reaching a valid 1. X means that a reliable binary interpretation is not guaranteed here. The capacitor still has a definite calculated voltage.
A NAND gate puts its nMOS devices in series: both inputs must be high to complete the pull-down. Its pMOS devices are parallel, so either low input can enable a pull-up. A NOR gate exchanges those series and parallel arrangements. Either high input completes a pull-down. The connections implement the logic. MIT: CMOS technology and timing
How are the curves calculated?
An enabled channel is a finite resistor; a disabled channel is an open circuit. The model traverses the actual graph, verifies that the output connects to exactly one supply rail, then solves internal-node current balance to obtain equivalent resistance. Truly disconnected internal nodes remain floating. Internal-node capacitance is omitted; output capacitance is retained throughout.
An input event changes the resistor network, but each segment starts at the previous segment’s final voltage. Charge remains continuous. Exact exponential segments reconstruct any requested time from a deterministic event schedule.
The teaching defaults are 1.2 V, 20 fF and 5 kΩ per enabled channel. An inverter has a 100 ps time constant and takes about 69.3 ps to reach half supply from either rail. Two equal pull-down resistors in series double that time; two parallel pull-up resistors halve it. These are results of the declared circuit, not measured chip specifications.
Why separate a switching boundary from a logic label?
The film labels V ≤ 0.3 VDD as 0 and V ≥ 0.7 VDD as 1, with X between them. The cascade separately uses 0.5 VDD to select the next stage’s ideal switches. It can therefore begin responding while Y₁ still reads X. Those markers serve different purposes. Real input/output guarantees and transistor thresholds depend on technology and device specifications; these teaching numbers are not universal.
This model does not solve MOSFET gate-to-source voltage, nonlinear current curves, or partial simultaneous conduction. Equal pMOS and nMOS resistance is an authored comparison condition. The first stage’s output capacitance already includes its wire and downstream gate load; connecting the second stage does not count that load twice.
Where does switching energy go?
Charging from zero to the supply rail puts half the supplied energy into the capacitor and dissipates half in the pull-up resistance. Discharging releases the stored half as heat in the pull-down. A sufficiently settled cycle with the defaults consumes about 28.8 fJ. The film allows twelve time constants per half-cycle and displays finite-time integrals, so it approaches rather than imposes that limit.
Zero permanent DC current at an ideal settled level does not mean zero static power in a real chip. Leakage, switching overlap, input-driver energy and additional parasitics are outside this model. Real CMOS power accounting includes those contributions. TI: CMOS Power Consumption and CPD Calculation